1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device including a memory transistor with a composite gate structure and to a method of manufacturing the same. Particularly, it relates to a non-volatile semiconductor memory device including memory transistor with a composite gate structure, such as an EEPROM or flash memory, and to a method of manufacturing the same.
2. Description of the Related Art
A normal semiconductor device is operated by a power supply voltage of about 3 to 5 V, whereas a non-volatile semiconductor memory device such as an EEPROM or flash memory sometimes needs a high voltage of 10 or more volts for operation of its inner circuit.
For example, in a floating gate EEPROM memory cell, the threshold voltage of the memory transistor changes depending on whether a given amount of electric charge is stored in the floating gate electrode of the memory transistor. The different threshold voltages are respectively determined correspondingly to data of "0" and "1" as stored.
The data in the memory cell can be rewritten by injection of electric charge from the drain into the floating gate electrode through the tunnel oxide film formed under the floating gate electrode, or by extracting electric charge from the floating gate electrode to the drain. For example, when potentials of 15 V and 0 V are, respectively, applied to the control gate electrode of the memory transistor and to the drain diffusion layer, and the substrate portion thereof, and the source diffusion layer is rendered to a floating state, electrons are injected from the drain diffusion layer into the floating gate electrode by the FN tunnel phenomenon through the tunnel oxide film. In addition, when potentials of 0 V and 15 V are, respectively, applied to the control gate electrode and the substrate portion, and to the drain diffusion layer and the source diffusion layer is brought to a floating state, electrons are extracted from the floating gate electrode to the drain diffusion layer by the FN tunnelling phenomenon through the tunnel oxide film.
The FN tunnel phenomenon mentioned above is effected generally more efficiently as the impurity concentration of the train diffusion layer is increased.
On the other hand, the rewriting operation of the memory cell is more efficient as the electric field applied to the tunnel oxide film is increased. In other words, the memory cell rewriting speed increases with an increase of the voltage applied to the drain diffusion layer. However, if a high voltage is applied to the drain diffusion layer, the avalanche phenomenon occurs in the PN junction between the drain diffusion layer and the substrate portion. Thus, the voltage that can be applied to the drain diffusion layer is limited by the avalanche breakdown voltage. For example, as disclosed in JP-A-60-110167, the avalanche breakdown voltage greatly depends on the PN junction between the drain and the substrate, and it is decreased with increase of the impurity concentration of the drain.
Also, as disclosed in JP-A-60-110167, when the impurity concentration of the drain is rendered higher, an electric field applied to the PN junction between the drain and the substrate becomes higher at the operation of reading out of data so that the hot carrier is greatly deteriorated, resulting in the reduction of its reliability.
In the prior art, as described above, there exists a problem that when the drain of the memory transistor is made with high impurity concentration in order to improve the rewriting speed in EEPROM or the like, the breakdown voltage of the PN junction between the drain and the substrate is decreased, resulting in decreased reliability against the hot carrier deterioration. On the contrary, when the drain diffusion layer of the memory transistor is made with lower impurity concentration to raise the breakdown voltage of the PN junction between the drain and the substrate to improve the reliability against the hot carrier deterioration, the rewriting speed of the memory cell is reduced.
In short, the improvement in the rewriting speed of EEPROM or the like, and the improvement in the breakdown voltage of the PN junction between the drain and the substrate and the reliability against the hot carrier deterioration are a trade-off with each other and no technique for satisfying both at the same time has heretofore been developed.
In addition, as disclosed in JP-A-63-301566, and "Reliable Profiled Lightly-Doped Drain (PLD) Cell for High Density Submicron EPROMs and Flash EEPROMs" by K. Yoshikawa et al., Abstracts of the 20th (1988 International) Conference on Solid State Devices and Materials, Tokyo, 1988, pp. 165-168, a PLD cell is proposed for preventing the reduction of the reliability of EEPROM by suppressing the tunnel leakage current between bands. However, the PLD cell is a memory cell in which data is written by hot electron injection, and it is required to provide the gate electrode with sidewalls to be used as a mask when forming the impurity diffusion layers formed by ion injection. This increases the number of processes for manufacturing EEPROMs.